---------------------------------------------------------------------------------- 
-- Module Name:    LUPOSkel - Behavioral 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LUPOSkel is
  port (
    LED        : out STD_LOGIC_VECTOR (7 downto 0);
    LVDS_CLKn  : in  STD_LOGIC;
    LVDS_CLKp  : in  STD_LOGIC;
    LVDSn      : in  STD_LOGIC_VECTOR (15 downto 0);
    LVDSp      : in  STD_LOGIC_VECTOR (15 downto 0);
--    LVDSn      : out STD_LOGIC_VECTOR (15 downto 0);
--    LVDSp      : out STD_LOGIC_VECTOR (15 downto 0);
    A          : in  STD_LOGIC_VECTOR (7 downto 0);
    CLOCK      : in  STD_LOGIC;
    INIT       : in  STD_LOGIC;
    IP0        : in  STD_LOGIC;
    IP         : in  STD_LOGIC_VECTOR (3 downto 0);
    UDI        : in  STD_LOGIC_VECTOR (3 downto 0);
    UDO        : out STD_LOGIC_VECTOR (3 downto 0);
    IRQ        : out STD_LOGIC;
    OP         : out STD_LOGIC_VECTOR (3 downto 0);
    RD         : out STD_LOGIC_VECTOR (31 downto 0);
    WR         : in  STD_LOGIC_VECTOR (31 downto 0);
    RD_STRB    : in  STD_LOGIC;
    WR_STRB    : in  STD_LOGIC);
end LUPOSkel;

architecture Behavioral of LUPOSkel is

component IBUFDS
  port (
    O  : out STD_LOGIC;
    I  : in  STD_LOGIC;
    IB : in  STD_LOGIC);
end component;

component OBUFDS
  port (
    I  : in  STD_LOGIC;
    O  : out STD_LOGIC;
    OB : out STD_LOGIC);
end component;

signal LVDSclk : std_logic;
signal LVDSio  : std_logic_vector(15 downto 0);


begin

LVDSINCLK_MAP : IBUFDS
  port map (
    O  => LVDSclk,
    I  => LVDS_CLKp,
    IB => LVDS_CLKn);


LVDSIN_MAPgene : for i in 0 to 15 generate
LVDSIN_MAP : IBUFDS
  port map (
    O  => LVDSio(i),
    I  => LVDSp(i),
    IB => LVDSn(i));
end generate;


--LVDSOUT_MAPgene : for i in 0 to 15 generate
--LVDSOUT_MAP : OBUFDS
--  port map (
--    I  => LVDSio(i),
--    O  => LVDSp(i),
--    OB => LVDSn(i));
--end generate;


clock_proc : process(CLOCK)
  begin
    if(CLOCK'event and CLOCK = '1')then
    end if;
  end process clock_proc;

end Behavioral;